ANALOG TESTING METHODOLOGY

As part of the design of the aether1/2 chips, numerous BIST (built-in-self-test) circuits were incorporated for externally probing and driving various subcircuits. We found several problems with this approach. First, it was very time-consumptive to modify existing cells to include BIST, and the physical layout of the entire chip took much longer. Of more import, it was difficult to probe the low noise logic, and even more difficult to probe internal nodes without significantly reducing performance - even when not being monitored. We chose to build in sense amplifiers that could convert the low level (< 1 volt) differential low noise logic signals to standard CMOS levels. These amplifiers can be powered down for low noise operation, or powered up for probing "in circuit" signals at nearly full speed operation. This approach may be needed for volume manufacturing, but it proved inappropriate at this stage because we really needed to measure analog voltages and currents. These include bias voltages and currents and differential and common mode signal levels.

From our experience with testing the aether2 chip, we developed a new methodology for testing our designs. The first principle is: don't try to probe the internals of a working system. Instead, make copies of the subsystems on the same chip, probe the interface signals of these subsystems; then iterate until the smallest circuits are being probed. When the chip is tested, if a large subsystem checks out, there is no need to analyze its subsystems. But if a large subsystem does not work, then the problem can be traced to its smaller components. Other goals were:

Using these principles, we came up with a system whereby signals could programmatically be switched using transmission gates (controlled by bits in a large serial shift register) to 16 different analog bus lines that connect to bonding pads. The analog bus lines are arrayed in two groups of 8 lines on either side of a row of circuits to be tested. The circuits are simply dropped in and wired to nearby transmission gates, which are connected to individual analog bus lines. The choice of which analog bus to use is done in the layout by dropping a via on the respective metal2 bus line. By setting the serial shift register bits under software control, we can interconnect, drive, and probe the desired circuit(s). We call this combination of analog bus lines and serial shift registers a "rail". If a circuit being tested needs a digital input signal, then a serial shift register bit can be used directly.

The compromise with this approach is that circuits cannot be tested at full speed because of the loading from the rails and the package. In cases such as testing a VCO, local buffering of the output can allow the circuit to operate while observing the output, albeit at reduced levels. In other cases, we have used the rails to setup and control a circuit, and used dedicated pads to drive and/or probe the circuit.

Using this approach, we have sped up our design and layout process significantly, and have submitted for fabrication one or more test chips per month since February 1995. This has allowed us to incrementally design, lay out, and test on a rolling basis all of the circuits that go into a complete transceiver.

DYNAMIC SHIFT REGISTER

The heart of this system for building test chips is a 12-transistor serial shift register, partially dynamic and partially static, that is a mere 44 x 20 microns in size, and needs only two control signals plus a serial in and out. The circuit shifts dynamically using a single phase Clock signal. There is also a Keep control signal. When asserted, Keep transfers the shift data to the register output and switches to a static hold mode. In other words, the output of the shift register does not change while shifting. This prevents conflicting settings of the transmission gates and circuit inputs controlled by the shift string. In addition, by setting Keep high and Clock low at power-on, the shift registers are reset to output low.

TESTING SYSTEM

We considered using commercial A/D and D/A boards in a PC for controlling the testing of our chips, but we found none that could be configured to programmatically probe, drive, or disconnect each chip pin. Since A/D and D/A IC's are now available with multiple channels and serial data inputs and outputs, we built our own interface board for testing chips. It connects to a PC over a parallel printer cable, and provides serial data to the conversion chips, address and control signals, and signals for loading the serial shift string inside our test chips.

In-house software had to be written to test chips on this system. To avoid errors in describing the chip to the test software, we wrote a program that reads the PSpice schematic files directly, and produces a description of each test chip. With a description of a component, the technician uses a second testing program to drive the A/D and D/A converters. This test program can drive the pins with values from vector files in traditional digital testing methodologies, or run pins through analog sweeps, or combinations of the two. Interactive commands can be used to execute the component, or a long series of test values can be written to files. These output files can be pasted into mathematical analysis programs, such as Mathcad, to analyze the results, plot graphs, and print reports.
 
 

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