HARDWARE OVERVIEW

We have taken a systems approach to the design of Localizers. We perform only the most time-critical and processing-intensive functions in hardware, and bury most of the system complexity in software. As much as possible, the sequential operation of the hardware is controlled by a general purpose processor. This way, the details of operation can be worked out over time, and can be quickly changed if there are unanticipated problems. For transmission, the basic task is sending coded sequences of Gaussian impulses at precise times. For reception, the basic task is correlating the antenna signal against a known code sequence with precise alignment in time.

FIGURE 15. Block diagram of the Localizer hardware. Shaded lines represent low noise differential signals, and shadowed boxes represent circuits implemented with low noise logic.

REAL TIME CLOCK

To precisely trigger an event in time to 30 ps resolution, one would ordinarily need a 33 GHz clock and a counter capable of operation at this frequency. This would require Gallium Arsenide logic and be very power consumptive. Our approach obviates this problem by using the very high short term stability of crystal oscillators and the repeatability of conventional logic. The idea is to subdivide the period of a crystal oscillator into much finer graduations. In fact, this is done in several steps.

We start with a crystal oscillator running continuously at a frequency that is not too power consumptive (nominally 6.25 MHz). The signal from this oscillator is used to constantly clock the coarse resolution part of a Real Time Clock counter. A few milliseconds before a scheduled event, a voltage controlled ring oscillator (VCO) running at 200 MHz is phase-locked to the crystal oscillator. The divide-by-N counter in the feedback path of the phase-locked loop (PLL) is used as the high resolution part of the Real Time Clock counter. The 5 ns period of the VCO is further divided by selecting a tap around the ring, and by using a programmable delay generator with 30 ps (or finer) resolution.

PHASE-LOCKED LOOP

The Phase-Locked Loop (PLL) is composed of the following components: Except for the divide-by-N counter, these components have their own supply pads, and they are in separate islands surrounded by guard rings which also have separate supply pads.

The VCO is an 8-stage ring oscillator implemented with the same differential current-steering buffers as are used for the other low noise circuits. The buffer delays are controlled by varying the tail currents through the differential pairs. As such, the VCO circuit includes a voltage-to-current converter that linearizes the voltage-to-frequency response of the ring oscillator.

The phase comparator is a conventional digital phase-frequency detector with Up and Down outputs for controlling a charge pump. It is implemented with single-ended current-steering NOR gates. The charge pump uses differential pairs that switch current sources between the output and an internal node. The internal node is biased at the same voltage as the output to minimize signal dependent charge injection when the current sources are connected to the output. Simulations have shown that the phase error versus output charge transfer function is smooth and continuous through the origin. In other words, there is no deadband, as is usually the case with a digital phase comparator.

The loop filter is implemented as a lag-lead network on-chip using a polysilicon resistor and poly1/poly2/metal1/metal2 capacitors over N-well. The second order capacitor is 200 pf in order to close the loop with a natural frequency of 12.6 KHz using 1 uA of output current from the charge pump. Despite its size, the loop capacitor is kept on chip to prevent "wow and flutter" in the VCO frequency due to different on-chip and off-chip ground potentials.

The divide-by-N synchronous counter in the feedback path of the PLL also serves as the high frequency segment of the Real Time Clock. It can be set to divide by 16, 32, or 64, for operation of the VCO at 200 MHz with either a 12.5 MHz, 6.25 MHz, or 3.12 MHz crystal reference.

LINEAR FEEDBACK SHIFT REGISTER

The same type of pseudo-random noise (PRN) code sequence generator is used for both the transmitter and receiver sections. The design is a fully programmable 25-stage LFSR (Linear Feedback Shift Register). It is a universal code generator capable of generating Maximal Sequences (up to (2^25)-1 bits long), Kasami Small codes (256-member families up to 65,535 bits long), Kasami Large codes (32,800-member families up to 1023 bits long), Gold and Gold-like codes (4097-member families up to 4095 bits long), and more. To use the code sequence generator, the processor has to initialize registers with the polynomial value, the seed value, and the sequence length.

Gold codes, for instance, are often described as the XOR of two Maximal Sequences of length 2n-1, which can be generated by an LFSR of size n. The 2n+1 different members of a Gold code family, for a given pair of Maximal Sequences, are formed from the 2n-1 different alignments of the Maximal Sequences, plus the two sequences themselves. It turns out that a single LFSR of size 2n can generate Gold codes of length 2n-1 by using the polynomial which is the product of the polynomials for the constituent Maximal Sequences. The particular Gold code which is generated depends on the seed value used to initialize the LFSR. In other words, when the product polynomial is used, the LFSR will be stuck in one of 2n+1 subcycles. This same scheme works for Kasami codes using the product of two or three polynomials.

For maximum performance, the 25-stage LFSR is implemented in the Galois configuration. In this arrangement, each input Dn is either output Qn-1, or Qn-1 XOR Q25, as determined by the polynomial coefficient for the particular code. Other than the CMOS latch for the polynomial coefficient and the seed bit, the logic for each stage is merged into a single complex differential current-steering flipflop.

To further minimize switching noise, the clocks to the flipflops in the LFSR are staggered. This tends to smooth out the residual current surges drawn from the supplies. The clock signal ripples through 5 buffers, and the output of each buffer is further buffered to drive 5 stages of the LFSR. The earliest clock signal is used for the last stage of the LFSR. The output of the last stage is latched for one-half clock cycle before being fed back to earlier stages. This prevents the feedback signal from changing before the clock signal reaches the earlier stages.

TRANSMITTER SECTION

The antenna-driving output of the transmitter section looks like a standard H-bridge, as is commonly used to drive stepping motors (Fig. 16). Each bit in the code sequence determines whether the current initially flows one way or the other through the bridge. The current through the antenna is turned on by connecting opposite sides of the antenna to VDD and VSS. The current is turned off by connecting both sides of the antenna to the same supply, VDD or VSS, which means there is always a closed path for current to flow. In other words, we generate a step change in current through the transmit antenna by causing a step change in voltage across the antenna. Our experiments have proved that this works. In effect, the "radiation resistance" makes the transmit antenna look like a resistor (of about 2 ohms) while the voltage is switching.

To generate an impulse doublet, the two sides of the transmit antenna are first switched to different "supply" voltages and then switched to the same "resting" voltage. Ideally, the resting voltage is midway between the supply voltages, so that the average voltage of the transmit antenna does not have to change. Ordinarily, this would require a positive and negative supply with a common ground. With a single supply, the resting voltage has to be either VDD or VSS. We have incorporated in the antenna-driving circuits four options for selecting the resting voltage. Two of these options seek to balance how often the resting voltage is VDD and how often it is VSS.

For switching current through the transmit antenna, MOS transistors work better than bipolar transistors (even though their current gain is less than bipolar for a given size), because they can be turned off as rapidly as they are turned on. Since it is only the switching edge speed that is important, we can cascade a series of exponentially-sized CMOS inverters to drive the final stage. The actual delay through this driver chain is not important as long as it is stable and repeatable, and the final stage is driven as fast as possible.

Each of the four arms of the 'H' bridge has two programmable delay elements (one for each edge) to adjust making and breaking the switch connection in the respective output transistor. This can compensate for the different switching delays of the P-channel versus N-channel transistors, and for other circuit mismatches. Experiments have shown that there can be considerable "ringing" in the transmit antenna, which does not happen when the making and breaking of the switch connections are carefully aligned.

Each arm is also divided into multiple (>= eight) sections which can be individually enabled for power control. Multiple bond pads are allocated to the driver outputs to minimize bond wire inductance. The P-channel and N-channel output transistors are isolated from each other by guard rings and physical separation to prevent latchup. Substantial on chip capacitance is interwoven with the drivers to ameliorate the effect of the bond wire inductance for the supply connections.

FIGURE 16. Block diagram of the transmitter antenna drivers. A typical section is shown in detail to illustrate the 'H' bridge configuration of output transistors which drive the transmit antenna. There are eight to twelve sections which can be separately enabled for adaptive power control.


RECEIVER SECTION

The receiver section includes the receiving antenna amplifier, the code sequence generator, and the Time-Integrating Correlator (TIC) with 32 integrators The receiving antenna amplifier and the code sequence generator feed the Time-Integrating Correlator (TIC) with the amplified received signal and the reference code respectively.

A high gain amplifier with sufficient bandwidth to handle 1 nanosecond impulses is difficult to design in current CMOS technology. The maximum bandwidth is achieved by having a cascade of multiple stages with a small amount of gain and wide bandwidth per stage. The overall gain is the product of the gain of each stage. However, the overall frequency response is also the product of the frequency response for each stage. So there is an optimum gain per stage, which based on simulations is not surprisingly about 2.7 (i.e. e).

In 2 micron (2µ) CMOS we have designed and tested a DC-coupled differential gain block with variable gain up to 6 dB, flat frequency response to 300 MHz, and unity gain at 900 MHz. In 1.2µ CMOS we have designed and simulated a DC-coupled differential gain block with 10 dB gain and flat frequency response to 800 MHz. In these simulations we were able to optimize the transistor parameters so that a cascade of 6 stages had 62 dB of gain with ~1.6 dB of peaking in the frequency response. To actually achieve this performance in silicon, the frequency response of individual stages must be adaptively controlled.

The receiver section uses the same circuitry as the transmitter section for generation of the code sequence at a nominal 100 MHz chip rate (200 MHz Gaussian impulse rate). The same code sequence is fed to each integrator in the TIC, but delayed by a different amount for each "phase". A phase corresponds to an integration window 5 ns wide, but the phases are spaced 2.5 ns apart, so that their windows overlap. The integrators are implemented using a differential transconductance amplifier with a floating poly1/poly2 capacitor across the outputs. Multiplication by the code sequence is done by multiplexing the two sides of the differential received signal to the differential inputs of the integrator. To multiply by zero, the integrator inputs are muxed to the same mid-voltage. Due to the finite impedance of the current sources in the integrators, the integrator outputs have to be sampled at the end of the code sequence. The Sample-and-Hold (S/H) circuits serve this purpose, and also serve the function of buffering the integrator outputs. The outputs of the S/H circuits are muxed onto a common analog bus to be digitized by the A/D converter, which is read by the processor.
 
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