MILESTONES

The major milestone for the next six months is the integration of the chips and software we have developed with a commercial processor, and to construct a pager-sized technology demonstrator unit for delivery to ARPA. The tasks we need to perform for this include:

Adapting the current test system for the transmitter and receiver chips in fabrication;
Testing and revising the transmitter and receiver chips;
Porting of synchronization, ranging, and networking protocols from our simulator;
Coding and debugging neural networks to extend the detection range;
Design and debugging of the processor board for the pager-sized units.

With each new revision of our transmit and receiver chips, we will put more circuits on chip. These will include:

Circuits that we have deferred developing because their functions could be done using commercial parts, including and A/D converter, crystal oscillator, and voltage references;
Revised versions of our receiver amplifier to improve the sensitivity, noise performance, and dynamic range;
Floating gate circuits for adaptively canceling input offsets and for tuning frequency response (versus the dynamic adjustment via DAC's which is now implemented).

FIGURE 2. Transmitter Driver chip (nstest11) can switch 2 amps in 500 ps across the transmit antenna. The Nchannel and P-channel transistors on both sides form an H-bridge configuration. There is an adjustable delay for both the positive and negative edges of the signals going to all 4 legs of the Hbridge. The output power is controlled by enabling any combination of 8-12 output sections. Multiple bond pads minimize the inductance connecting to the transmit antenna. This chip is driven by the Receiver/coordinator chip (aether3), but it also includes a code sequence generator for stand-alone testing.

FIGURE 3. Receiver/coordinator chip (aether3) includes all the subsystems for reception of ultra-wideband signals, and drives the Transmitter Driver chip (nstest11) for transmission. The major components are a 200 MHz phase-locked loop, a multi-stage Real Time Clock for triggering transmit and receive events, dual code sequence generators for both transmit and receive, an 800 MHz broadband receiver antenna amplifier with 60dB gain, and 32 Time Integrating Correlator phases/integrators for detecting long code sequences.

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