NOISE REDUCTION
Our Localizer technology was under development for three years prior to
the start of sponsorship by ARPA in January of 1994. We had lab bench Localizers
made with our own custom CMOS chips and other commercial chips on PC boards.
An explicit goal of this project is integration of our circuits with the
functions performed by the commercial chips into a single chip. Our experience
with these PC board Localizers shows that a single chip Localizer is
not only desirable, but necessary to reach the performance specifications
we have set. These are submeter range accuracy over 100 meter
distances in real time for this phase of the project, and eventually centimeter
range accuracy over 1 kilometer distances.
Currently, the primary limitation on the distance we can communicate
is self-generated noise. This noise reduces the signal to noise
ratio (SNR) of the received signal and affects the stability of the timing
circuits, e.g. the phase-locked loop (PLL). Significant noise
sources include:
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VDD and VSS currents from the 200 MHz digital logic flowing off-chip and
coupling into the receiver antenna.
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PC board logic signals that switch during the 10 ms transmission and reception
window
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Digital logic in the correlator
Two conventional ways of dealing with self-generated noise are shielding
and physically separating the front end of the receiver from the noisy
circuits. Our experience is that shielding is particularly ineffective
against extremely broadband noise being picked up by extremely broadband
circuits. Using an antenna preamplifier that is physically separated from
the noisy circuits (i.e. on a separate chip) defeats the goal of
having a single chip transceiver.
Self-generated noise is an inherent problem for nonsinusoidal communication
systems, because the correlator and logic circuits have to operate with
edge speeds and clock rates that are in the same frequency range as the
actual transmitted and received signals. Sinusoidal systems (such as GPS)
avoid this problem by doing all their digital processing at a much lower
frequency than the carrier frequency - the received signal is immediately
down-converted to an intermediate frequency or baseband.
We face the problem of self-generated noise head-on in this project
in several ways:
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By migrating the circuitry that has been on the PC board on-chip,
we eliminate the high current signals and large dipole moments.
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In place of conventional (noisy) CMOS logic circuits, we use current-steering
and other low noise logic for those circuits which must operate during
the critical 10 ms reception window.
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We turn off (i.e. stop the clock) for all conventional CMOS logic
(including the processor) during the critical reception window.
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For those circuits which must operate while transmitting (including the
PLL), we use noise immune differential logic circuits.
The current-steering low noise logic we use is inherently power consumptive,
although less so than static CMOS logic operated at 200 MHz. Static CMOS
logic can use very little power but is inherently noisy. This tradeoff
dictates that Localizers operate under two regimes with some overlap when
transitioning from one to the other. During the reception window, the low
noise logic is powered and operational, and all clocks to the static CMOS
logic are stopped. All other times, the static CMOS logic is operational,
and the low noise logic is powered down. Fortunately, current-steering
logic can be powered down by turning off its current sources.
LOGIC CIRCUITS
We use four types of logic. In addition to conventional static CMOS logic,
there are both single-ended and differential current-steering logic, and
differential series pass logic. Differential current-steering logic is
well suited to making flipflops. A D-type flipflop with Set/Reset inputs
and Q/Q* outputs requires only 24 transistors. A comparable flipflop in
static CMOS typically requires 35 transistors. Also, additional logic functions
can be merged into these flipflops with only a few more transistors. For
instance, a two-input multiplexer feeding the D input adds only 4 transistors.
We have discovered that conventional CMOS logic can be efficiently combined
with differential current-steering logic when the conventional logic is
used for effectively static signals. For example, polynomial coefficient
values are loaded by the processor into static latches that configure the
LFSR. These are never changed while the LFSR is operating.
We use 5-bit DAC's to set the bias currents for the current-steering
logic. This allows us to characterize the performance of the current-steering
logic, to adjust the speed/power tradeoff in different sections, and to
compensate for process variations.