RECEIVER

RECEIVER CHIP (aether3)

We have just submitted for fabrication a chip (aether3, Fig. 3) with the remaining subsystems for completion of transceivers that can demonstrate sub-meter range accuracy over 100 meter distances in real time. The major components in this chip include:

A 200 MHz phase-locked loop, in low noise logic;
All three stages of the Real Time Clock, with the high speed stages in low noise logic, including event registers and comparators for both transmit and receive;
Two code sequence generators, one each for transmit and receive, which includes a 25-stage programmable LFSR (Linear Feedback Shift Register), a 16-bit run-length counter, and a doublet generator, all in low noise logic;
32 Time-Integrating Correlator phases; each phase has a reference code latch, code/signal multiplier, integrator, offset correction, sample-and-hold, and output mux;
A broadband differential receiver antenna amplifier composed of six cascaded stages with 60 dB gain and flat frequency response to 800 MHz;
Eighteen 5-bit DAC's for biasing the low noise logic;
Processor interface including processor clock gating, parallel I/O decoding, and serial protocol control.

REGULATED FSCL

We reviewed several different types of low noise differential current-steering logic reported in the literature. We chose to use Folded Source-Coupled Logic (FSCL) because reports and our simulations showed that it generated the lowest noise current from the supply. From our experience using FSCL in the aether2 chip, we learned its limitations.

The input of an FSCL buffer is an N-channel differential pair. The output is a folded load consisting of a P-channel current source from VDD and a diode-connected transistor load to VSS. When fully switched, the current from VDD flows through the output load on one side, while on the other side the current is diverted through one of the differential pair transistors. The output swing is determined by the load and the tail current. Any excess current from VDD not switched through the differential pair sets the low output level.

The low-noise performance of FSCL is achieved by operating all of the family components (i.e. buffers, gates, flipflops, etc.) as class-A amplifiers. In other words, all of the current available for charging the output nodes is constantly being drawn from the supply. Decreasing the bias current to limit power consumption also reduces switching speed. Having low power consumption also limits fanout and the ability to drive long wiring loads.

For a given size load, there is a tail current that achieves the desired output swing. If the load is too small, the bias generator can increase the tail current, but only up to the point where the tail current transistor falls out of saturation. Erring on the side of making the load too large slows down the switching speed by increasing the parasitic capacitance of the load transistors, and by requiring a smaller tail current to maintain the desired output swing. Thus, inaccuracies in transistor modeling and variations due to processing and temperature can cause FSCL components to fail, making the output swing too small or the switching speed too slow.

To fix the problem with load-sizing in FSCL, we developed what we call Regulated Folded Source-Coupled Logic (RFSCL). We changed the diode-connected transistor load in the output legs of FSCL to a diode-connected transistor above a transistor operated in the linear region. We kept the diode-connected transistor because it adds a threshold of level shift, and makes it easier to keep the other transistor in the linear region.

The key to making RFSCL work is the bias generator which controls the load resistance and the tail current so that the low and high level outputs are regulated to fixed voltages. Because RFSCL has an extra degree of freedom in the control of the output load, it is possible to vary the bias current over a large range, effectively varying the switching speed. This allows us to adjust the speed of the RFSCL to match the needs of the circuit it is in. (In fact, we are able to use RFSCL buffers to form the ring oscillator at the core of the phase-locked loop.)

INTEGRATOR

A critical component of the Localizer system is the integrator at the heart of the Time-Integrating Correlator. It must have both sufficient bandwidth to handle 1 ns wide impulses and high enough output impedance to leak very little charge over a 10 ms period (the length of a thousand-chip code sequence). It must also have a very low input offset voltage. To achieve these goals, a number of new circuit topologies were explored.

The new integrator design is based on a folded cascode differential output transconductance amplifier. P-channel transistors are used for the input differential pair so that the common mode of the input signal can be biased low. This allows N-channel switches to be used for muxing the amplified receiver signals to the integrator inputs. Regulated cascodes are used for the P-channel current sources in the output legs because they have superior output impedance and only one threshold drop. An optimal bias for the N-channel cascode transistors in the output legs is derived from a regulated cascode current mirror. The bias for the N-channel current sources in the output legs is derived from the common mode feedback circuit. This configuration for the common mode feedback adds no additional voltage drop, thereby maximizing the differential output range.

Increasing the bias current for the integrator increases its bandwidth, but also significantly decreases its output impedance. At a bias current (20 µA) where simulations show the 1 dB bandwidth to be greater than 500 MHz, the output impedance is ~41 Megohms. At this bias, the transconductance is ~47 µmhos. This translates to an effective "impedance gain" of about 66 dB.

Because the Time-Integrating Correlator is not operated continuously, the input offset error of the integrator amplifiers can be automatically corrected before each operation of the integrators. The input offset is canceled by creating a negative feedback loop around the integrator amplifier, connecting to a much smaller differential pair wired in parallel with the amplifier inputs. Because the feedback loop includes an integrator, the input offset error is driven to zero. The differential correction signal is maintained in a track-and-hold (T/H) circuit while the integrators are operating. Several different circuits were tried for canceling the signal dependent charge injection in the T/H, but the extra active circuitry caused more leakage over time. We settled on using a simple transmission gate feeding a capacitor, with a dummy switch for charge cancellation.

SAMPLE-AND-HOLD

Each correlator phase includes a Sample-and-Hold (S/H) circuit for maintaining its integrator output while the processor does an A/D conversion on all 32 correlator phases. A compact high gain differential amplifier with differential output was designed for implementing the S/H function. The amplifier is based on a complementary folded cascode topology. It achieves 70 dB of DC gain in a single stage through the use of regulated cascodes in the output. The common mode feedback is efficiently merged with the feedback which closes the S/H loop. The physical layout is only 72 x 42 microns.

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