TESTING OF TRANSMITTER CHIP (aether1/2)

• The transmitter antenna drivers and control circuits;
• A 200 MHz phase-locked loop (in low noise logic);
• A 25-stage LFSR (Linear Feedback Shift Register, for pseudo-random pattern generation) in low noise logic, with programmable seed and polynomial registers;
• A 16-bit run-length counter in low noise logic, with preload register for the LFSR;
• The two highest speed portions of the Real Time Clock (in low noise logic);
• Twelve 4-bit DAC's for biasing the low noise logic and controlling 4 edge-delays;
• Extensive built-in test circuits for externally probing and driving various subcircuits;
• Processor interface including clock-gating and synchronizing.

DEVELOPMENT SYSTEM

• A motherboard with power regulation, D/A and A/D converters, fiber optic link, and interface logic;
• A COB (chip-on-board) daughterboard for the aether1 chip, plus regulators for voltage and current biases;
• A commercial daughterboard with a Motorola 68332 processor, RAM, and ROM.

The COB daughterboard was fabricated with polyamide so that the aether1 chip could be epoxied in a cavity and gold wire ball-bonded directly to the board. This eliminates the lead inductance of a chip package and minimizes the wire bond inductance, especially for the transmitter driver outputs. The transmitter antenna is clamped directly to gold-plated contacts on this board.

FABRICATION PROBLEMS

For noise isolation, we designed the aether2 chip with five sets of separate supply pins for different sections of the chip. Of the twelve chips we received from Orbit, every one had at least one of the five separate sets of supply pins shorted together. The problem was not in the design, because we were able to exercise all of the different sections on at least some of the chips. By forcing current through the shorted supply pins, we were able to identify the cause of the shorts as contacts to poly2 over poly1. These contacts are perfectly permissible by MOSIS scaleable rules as supported by Orbit, but apparently their process wasn't up to specifications, since the poly2 contacts were punching through the thin oxide separating poly1 and poly2. Even for the sections on particular chips that did not have their supplies shorted, our testing results were questionable, since many of our circuits used isolated poly1/poly2 capacitors.

We had Orbit test the 24 instances of aether2 that were on their backup wafers. The results were the same. At least one of the five separate sets of supply pins was shorted on each of the chips. In consultation with one of their process engineers, we also learned that they were modifying our mask layouts in a manner that could lead to design rule violations. To match MOSIS scaleable rules to their design rules, they were performing bloats of certain mask layers in a naïve manner. In addition, they were doing high temperature metal processing which forced metal1 busses to "squirt" through vias to metal2, thereby causing shorts on the metal2 layer.

We would have switched to another fabricator for our chips, but Orbit Semiconductor is the only choice for multi-project wafer runs in a 1.2µ analog CMOS process with floating capacitors. Instead, we modified our design rules (and our physical layout) to compensate for their processing problems. One, we disallowed contacts to poly2 over poly1. Two, we bloated our mask layers the same as Orbit, and then checked for spacing violations using Orbit's design rules. Since this is a more conservative check, our layouts are still scaleable, and can be fabricated by other foundries that may support MOSIS scaleable rules.

ANTENNA DRIVERS