TRANSMITTER CHIP (nstest11)
Last year, our development plans called for expanding the aether2 chip
to include receiving circuits in addition to the transmitting circuits
already on chip. We decided instead to put the transmitter antenna drivers
on a separate chip (nstest11, Fig. 2) for several reasons:
-
We wanted to electrically isolate the Phase-Locked Loop from the noise
generated by switching high currents through the transmit antenna.
-
Our experience with chip-on-board showed that we could reasonably wirebond
between two chips.
-
We wanted to preserve the aspect ratio of the transmitter drivers on the
aether2
chip
which minimized the wire bond inductance driving the transmit antenna.
-
The number of signals needed to go between chips is minimized if the transmitter
circuitry is divided just after the transmit waveforms are generated and
before they are amplified to drive the antenna.
-
The antenna drivers do not need floating capacitors, so they can be fabricated
using a single-poly process such as HP's 1.2µ, available through
MOSIS.
We will be able to build complete transceivers using the nstest11 chip
and the receiver chip described below. To facilitate early testing, nstest11
has additional circuitry for generating code sequences and antenna waveforms
given an external clock and start signal. This circuitry can be bypassed
when nstest11 is controlled by the receiver chip. The interface
with a processor or another chip is via a serial shift protocol.
EDGE DELAY
The programmable delay elements in each of the four arms of the 'H' bridge
were redesigned so that both the rising and falling edges of the transmit
waveform can be adjusted separately. This allows control of making and
breaking the switch connection in the respective output transistor, and
can compensate for the different switching delays of the Pchannel versus
Nchannel transistors.
For the programmable delay element, we needed a gate and a buffer that
would pass limited swing differential signals. The buffer would also have
to transition between set voltage levels with a linear ramp dependent on
programming current. This requirement that the output saturate at fixed
levels ensures that the delay is not dependent on the duty cycle of the
waveform passing through the buffer.
The new buffer is a complementary differential design with diode-connected
transistors that clamp the output swing. This design can be described as
current diverting as opposed to current steering. While switching, the
set bias current charges the output nodes until they reach full output
swing, at which point the clamping diodes divert the current away.